Integrated circuit memory devices, such as dynamic random access memories (DRAMs), include in each storage cell a transfer transistor and a capacitor for temporarily storing information. These devices have been increasing in the number of storage cells per device for many years. Each increase of storage capacity is made possible by shrinking the amount of space, i.e., the device surface area, occupied by each storage cell. Necessary shrinkage has been accomplished by shrinking storage cell components such as the transistor and the capacitor.
The capacitance of the capacitor is particularly important because the capacitor's ability to accurately store and read out bits of data is closely related to the quantity of charge stored in the capacitor. In the past, the capacitance has been kept high by forming three dimensional capacitors known, for example, as trench capacitors and stacked capacitors. More recently. designers have pursued forming capacitors having an insulator material with a high dielectric constant. Such materials have a dielectric constant much higher than the dielectric constant of familiar materials, such as, silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3 N.sub.4), and combinations thereof.
It is known that high dielectric constant materials, such as BaSrTiO.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.9 and Pb(ZrTi)O.sub.3, generally are not chemically stable when they are deposited directly on a semiconductor substrate. One or more additional layers of other materials are used to make an electrical connection between the high dielectric constant material and the substrate. For example. the storage node, or storage plate, is a bottom capacitor electrode made of conductive material, such as platinum (Pt), palladium (Pd), gold (Au), or other conductive material, that lies under the capacitor dielectric. The storage node is connected by way of a conductive contact, such as Al, an Al alloy, polysilicon, or doped silicon, to the source/drain electrode of the transfer transistor formed in the semiconductor substrate.
The additional layers of materials include a barrier layer, or layers, interposed between the high dielectric constant material and the substrate to prevent the diffusion of oxygen from the furnace atmosphere into the conductive contact when the high dielectric material is being deposited at temperatures of 500.degree. C. and greater. In accordance with the prior art, once the high dielectric material is deposited, the problem of oxygen diffusion into the conductive contact is solved because subsequent processing steps use lower temperatures and/or a non-oxidation furnace atmosphere. See for example, U.S. Pat. No. 5,504,041, which is incorporated herein by reference thereto.
Although the aforementioned problem has been resolved by the use of the barrier layers between the high dielectric constant material and the substrate, other problems continue to exist in the fabrication of integrated circuit devices which include high dielectric constant materials.
For instance noble metals, such as platinum, palladium, titanium and gold, are considered to be useful as the top, or plate, electrode of the capacitors using high dielectric constant materials like BaSrTiO.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.9 and Pb(ZrTi)O.sub.3. Those top electrodes are to be interconnected with a metallization layer made of aluminum or an aluminum alloy. Adverse interactions occur between the metallization layer and the high dielectric constant material during device processing steps including and following the deposit of the metallization layer. A barrier layer of titanium nitride (TiN) has been used between a platinum electrode and an aluminum metallization over SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT). A barrier layer of titanium tungsten (TiW) has been used between a platinum or titanium electrode and an aluminum metallization over Pb(ZrTi)O.sub.3 (PZT). A titanium nitride barrier layer is however unsuitable when an oxidizing annealing step is used in the fabrication sequence after etching the top electrode and barrier structure, since such oxidizing annealing step will cause oxidation and degradation of the titanium nitride barrier layer.